Technology scaling has been a main driving force behind the rapid advancement of the semiconductor industry. As part of the scaling efforts, state of the art processes for manufacturing smaller and higher performance transistors are continuously under development. For example, it is desirable to reduce the channel length of a transistor in order to increase the current capability of the transistor and to make the overall transistor size smaller. However, in scaling down the channel length, such barriers as junction breakdown and transistor punch through must first be overcome. Junction breakdown occurs when the electric field across a reverse biased junction becomes high enough to initiate avalanche impact ionization generation, resulting in a sharp current increase. In MOS technology, the junction breakdown voltage can be improved by reducing channel doping concentration and/or using lightly doped drain (LDD) and double doped drain (DDD) junctions.
Transistor punch through is defined as the drain voltage at which the drain depletion region extends all the way to that of the source region so that the source and drain regions become electrically shorted together. The transistor thus draws an undesirably high amount of current, resulting in prohibitively high leakage current or even the destruction of the transistor. The shorter the channel length is made, the lower is the drain voltage at which the drain to source punch through occurs. This can severely limit the operational voltages of integrated circuits. In order to improve punch-through effects, the channel doping concentration may be increased; however, this in turn leads to a lower junction breakdown voltage.
One of the factors influencing the extent to which the drawn gate feature or gate line width can be scaled is the amount of the gate overlap with the source/drain (S/D) regions that a process can tolerate. Clearly, the smaller the overlap, the smaller can the gate feature be made. Achieving a small overlap is a difficult task because of the inherent side diffusion of the source and drain regions during S/D implant activation and anneal.
This limitation on scaling of MOS transistors is even more pronounced in scaling of non-volatile memory cells. This is because such features of the non-volatile memory cell as the floating gate tunnel oxide and the interpoly dielectric layer (e.g., oxide-nitride-oxide (ONO) multilayer) are not readily scalable due to quality considerations of these insulating materials and the cell charge retention constraints.
As an example, a simplified conventional process sequence for a stack gate flash memory cell includes: forming a tunnel oxide over a substrate; forming a floating gate (poly 1) over the tunnel oxide; forming an interpoly ONO dielectric composite layer; and forming a control gate (poly 2 and tungsten silicide) over the ONO dielectric. In modern technologies, the control gate is often formed simultaneously with the gates of peripheral (CMOS) transistors, followed by cell self-aligned etch (SAE) of poly 1 using poly 2 as a mask. After formation of the polysilicon stack, a re-oxidation thermal cycle is performed. In subsequent steps, DDD implanting steps are performed for periphery high voltage (HV) NMOS and PMOS transistors, followed by oxidation and anneal cycles.
Next, the cell S/D implant (in case of symmetrical S/D cells) is performed followed by forming oxide spacers along the side-walls of both the cell polysilicon stack the periphery transistor gates. The properties and physical characteristics of the source and drain regions are dependent on the thickness of the screen oxide (i.e., oxide previously deposited covering the substrate surface areas where the source and drain regions are formed) through which the S/D implant is performed, the implant dose and energy, and the thermal activation. The room for optimizing the source and drain regions is limited. The S/D implant dose has to be sufficiently high to ensure low source and drain resistance, and the implant energy needs to be optimized based on the screen oxide thickness and the junction vertical depth requirements. The above parameters along with the thermal budget of S/D activation/anneal determine the extent of the overlap between the poly stack and the S/D regions, and thus the minimum effective channel length.
As indicated earlier, scaling of the thickness of the tunnel oxide and ONO dielectric layers are substantially limited. To reduce the gate length without scaling down the tunnel oxide and the ONO dielectric layers requires formation of sufficiently deep S/D junctions (e.g., junction depth of 0.07-0.1 xcexcm for gate length of 0.15-0.20 xcexcm) to ensure proper functioning of the cell. Sufficient junction depth is needed for lowering source/drain resistance, and achieving the desired overlap with the gate. The gate overlap should be sufficient for proper programming, read efficiency, and reliability considerations, yet small enough to provide for sufficient effective channel length, especially for very short gate feature. As such, the lateral junction depth, and thus the overlap between the polysilicon stack and the S/D regions are predetermined and limited by the S/D implant and thermal activation requirements.
For drawn gate length of 0.2 xcexcm, and maybe even 0.15 xcexcm, the effective channel length (which equals the drawn gate length minus the overlaps between the gate and the S/D regions) may be sufficient for proper functioning of the cell (i.e., without punch-through and with high enough junction breakdown voltage BVdss), provided the channel doping is properly optimized. However, for gate length of about 0.12 xcexcm and shorter, the effective channel length becomes too short, or practically disappears. The cell will exhibit punch-through at very low drain voltage, preventing the cell from proper functioning.
Even highly advanced flash technologies with memory cell gate length of 0.1 xcexcm or shorter, require a drain voltage of 3-5V to ensure sufficient programming speed by channel hot electron injection. However, for such small gate features and voltage requirements, the above-mentioned adverse short channel effects can not be properly addressed only by optimizing the source/drain implant conditions and channel doping.
In accordance with the present invention, an off-set spacer is introduced in the process steps for manufacturing memory cells and transistors and the resulting structures which enables dramatic scaling of the channel length such that high performance transistors and memory cell structures with extremely small gate feature and overall size that exhibit robust program/erase efficiency and read speed, and enable low operating voltages, can be manufactured.
In one embodiment, a method of forming semiconductor transistors includes: forming a gate electrode over but insulated from a semiconductor body region; forming off-set spacers along side-walls of the gate electrode; and after forming said off-set spacers, forming a source region and a drain region in the body region so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers.
In another embodiment, said gate electrode forming act includes forming a gate electrode for each of first and second transistors, and said off-set spacers forming act includes forming off-set spacers along side-walls of the gate electrodes of the first and second transistors, said source and drain regions forming act further comprising performing a DDD implant to from DDD source and DDD drain regions for the first transistor.
In another embodiment, the method further includes: performing a LDD implant to form LDD source and LDD drain regions for the second transistor; after both said DDD and LDD implants, forming main spacers adjacent the off-set spacers of the first and second transistors; and after forming said main spacers, performing a source/drain (S/D) implant to form a highly doped region within each of the DDD drain and DDD source regions and each of the LDD drain and LDD source regions, the highly doped regions being of the same conductivity type as and having a doping concentration greater than the DDD and LDD regions.
In another embodiment, the extent of an overlap between the gate electrode of the first transistor and each of the DDD source and DDD drain regions, and the extent of an overlap between the gate electrode of the second transistor and each of the LDD source and LDD drain regions is inversely dependent on a thickness of the off-set spacers, and wherein a distance between an outer edge of each of the DDD source and DDD drain regions and an outer edge of the highly doped region within each of the DDD source and DDD drain regions is directly dependent on a thickness of the main spacers, and a distance between an outer edge of each of the LDD source and LDD drain regions and an outer edge of the highly doped region within each of the LDD source and LDD drain regions is directly dependent on a thickness of the main spacers.
In another embodiment, a method of forming a non-volatile memory cell includes: forming a first polysilicon layer over but insulated from a semiconductor body region; forming a second polysilicon layer over but insulated from the first polysilicon layer; forming an off-set spacer along at least one side-wall of the first and second polysilicon layers; and after forming said off-set spacer, forming at least one of source and drain regions in the body region so that the extent of an overlap between the first polysilicon layer and said one of source and drain regions is dependent on a thickness of the off-set spacer.
In yet another embodiment, the first and second polysilicon layers form a polysilicon stack, off-set spacers being formed along side-walls of the polysilicon stack, and source and drain regions being formed after forming the off-set spacers so that the extent of an overlap between the polysilicon stack and each of the source and drain regions is inversely dependent on a thickness of the off-set spacers.
In another embodiment, a method of forming a non-volatile memory cell and transistors includes: forming a first polysilicon layer over but insulated from a semiconductor body region, and a second polysilicon layer over but insulated from the first polysilicon layer, the first and second polysilicon layers forming a polysilicon stack of the memory cell; forming a gate electrode for each of first and second transistors over but insulated from a semiconductor region; forming off-set spacers along side-walls of the polysilicon stack and the gate electrode of the first and second transistors; and after forming said off-set spacers, forming source and drain regions for each of the memory cell and the first and second transistors so that the extent of an overlap between the polysilicon stack and the cell source and drain regions and the extent of an overlap between each of the gate electrodes of the first and second transistors and their corresponding source and drain regions are dependent on a thickness of the off-set spacers.
In another embodiment, the method further comprises: performing a DDD implant to form DDD source and DDD drain regions for the first transistor; and performing a LDD implant to form LDD source and LDD drain regions for the second transistor.
In another embodiment, the method further includes: performing a cell source/drain (S/D) implant to form the cell source and drain regions; and after said cell S/D implant and said LDD implant and said DDD implant, performing a transistor S/D implant to form highly doped regions within all the DDD and LDD regions.
In another embodiment, the method further includes: after said cell S/D implant and said LDD implant and said DDD implant but before said transistor S/D implant, forming main spacers adjacent the off-set spacers of at least the first and second transistors, wherein the highly doped regions within all the DDD and LDD regions are of the same conductivity type as and have a doping concentration greater than the DDD and LDD regions.
In another embodiment, a structure includes a first transistor which includes: a first gate electrode over but insulated from a semiconductor body region; off-set spacers along side-walls of the first gate electrode; and a source region and a drain region in the body region so that the extent of an overlap between the first gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers.
In another embodiment, the structure further includes a second transistor which includes: a second gate electrode over but insulated from a semiconductor body region; off-set spacers along side-walls of the second gate electrode; source and drain regions; main spacers adjacent the off-set spacers of the first and second transistors; and wherein each of the source and drain regions of the first transistor comprises a highly doped region within a DDD region, and each of the source and drain regions of the second transistor comprises a highly doped region within a LDD region, the highly doped regions being of the same conductivity type as and having a doping concentration greater than the DDD and LDD regions.
In another embodiment, the extent of an overlap between the first gate electrode and each of the DDD source and DDD drain regions, and the extent of an overlap between the second gate electrode and each of the LDD source and LDD drain regions is inversely dependent on a thickness of the off-set spacers.
In another embodiment, a distance between an outer edge of each of the DDD source and DDD drain regions and an outer edge of the highly doped region within each of the DDD source and DDD drain regions is directly dependent on a thickness of the main spacers, and a distance between an outer edge of each of the LDD source and LDD drain regions and an outer edge of the highly doped region within each of the LDD source and LDD drain regions is directly dependent on a thickness of the main spacers.
In another embodiment, a non-volatile memory cell includes: a first polysilicon layer over but insulated from a semiconductor body region; a second polysilicon layer over but insulated from the first polysilicon layer; an off-set spacer along at least one side-wall of the first and second polysilicon layers; and source and drain regions in the body region, wherein the extent of an overlap between the first polysilicon layer and at least one of said source and drain regions is dependent on a thickness of the off-set spacer.
In another embodiment, the first and second polysilicon layers form a polysilicon stack, the memory cell further comprising off-set spacers along side-walls of the polysilicon stack so that the extent of an overlap between the polysilicon stack and each of the source and drain regions is inversely dependent on a thickness of the off-set spacers.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the present invention.